Field of the Invention
The embodiments of the invention relate generally to the field of computer processors. More particularly, the embodiments relate to an apparatus and method for system physical address to memory module address translation.
Description of the Related Art
1. Processor Microarchitectures
An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). It should be noted that the term “instruction” generally refers herein to macro-instructions—that is instructions that are provided to the processor for execution—as opposed to micro-instructions or micro-ops—that is the result of a processor's decoder decoding macro-instructions. The micro-instructions or micro-ops can be configured to instruct an execution unit on the processor to perform operations to implement the logic associated with the macro-instruction.
The ISA is distinguished from the microarchitecture, which is the set of processor design techniques used to implement the instruction set. Processors with different microarchitectures can share a common instruction set. For example, Intel® Pentium 4 processors, Intel® Core™ processors, and processors from Advanced Micro Devices, Inc. of Sunnyvale Calif. implement nearly identical versions of the x86 instruction set (with some extensions that have been added with newer versions), but have different internal designs. For example, the same register architecture of the ISA may be implemented in different ways in different microarchitectures using well-known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., the use of a Register Alias Table (RAT), a Reorder Buffer (ROB) and a retirement register file). Unless otherwise specified, the phrases register architecture, register file, and register are used herein to refer to that which is visible to the software/programmer and the manner in which instructions specify registers. Where a distinction is required, the adjective “logical,” “architectural,” or “software visible” will be used to indicate registers/files in the register architecture, while different adjectives will be used to designate registers in a given microarchitecture (e.g., physical register, reorder buffer, retirement register, register pool).
2. Memory Module Address Mapping
Servers in general and especially those used in enterprise and mission-critical computing demand a high level of serviceability. Memory is one of the most unreliable components in the system due to relatively high error rates. Servers are equipped with various error detection and correction technologies. Some servers may even predict a component failure before it happens, using Predictive Failure Analysis (PFA).
In some architectures, when an error occurs in the memory sub-system, hardware logs the associated address in the Machine Check (MCA) banks and other error log registers. This address is in System Physical Address (SPA) space. For memory-related errors, it is imperative to identify which physical dual in-line memory module (DIMM) to which this SPA is mapped in order to service the system.
Modern operating systems also record the DIMM serial number, and track SPAs which it will retire if an uncorrected error was reported in that region across boots. Apart from being useful for platform firmware based PFA, Enterprise and mission critical operating systems also require the SPA to DIMM translation to avoid tripping over memory regions that have previously encountered an uncorrectable error.
All these serviceability features require mechanisms to translate from the SPA into the DIMM Address. The DIMM Address will comprise of the Socket ID, iMC ID, Channel #, DIMM #, Rank ID, Bank, Row, and Column. This address translation is highly dependent on CPU design and it is not architecturally defined. This necessitates a new implementation for each processor generation.